1. Field of the Invention
The present invention relates to logic receivers, and more particularly to CMOS inverter-type receivers.
2. State of the Art
Logic receivers (also sometimes referred to as level shifters or input buffers) are used to accept an input signal and output a logic signal having a logic state representative of the voltage level of the input signal which can then be coupled to other logic circuitry. They can be classified as non-differential or differential in that they are either responsive only to an input signal (non-differential) or to the difference between two input signals (differential). An example of a differential receiver might be a differential amplifier. An example of a non-differential receiver might be as simple as an MOS switching device or a basic CMOS inverter. Although differential receivers tend to be more precise since they compare the input signal to a controlled reference signal, they also tend to require more circuitry to accommodate this type of comparison and accuracy. In contrast, non-differential receivers tend to require fewer elements and hence take up less space, but are less accurate than their differential counterpart due to device dependent operating fluctuations.
One important aspect of a receiver is its associated threshold voltage. The threshold voltage determines whether the input signal causes the input receiver to output a HIGH logic level or a LOW logic level. Specifically, if the input signal is higher than the threshold voltage, the receiver outputs a voltage corresponding to a first logic state and when the input signal is lower than the threshold voltage, the receiver outputs a voltage corresponding to a second logic state. Hence, the threshold voltage determines the accurate interpretation or detection of the input signal. Other important aspects of prior art receivers are their speeds, gains, and power dissipations.
FIG. 1 shows a typical prior art differential receiver as disclosed in U.S. Pat. No. 4,937,476 which includes two parallel inverters (device pairs 61/62 and 66/67) coupled between two biasing devices (64 and 65). The first inverter has its input coupled to a reference voltage (Vref) and its output signal (Vbias) coupled to the gates of the biasing devices 64 and 65. The biasing devices establish bias voltages on two summing nodes 71 and 72 so as to bias the second inverter such that its threshold voltage is equal to the reference voltage coupled to the input of the first inverter. The second inverter has its input coupled to the input signal (Vin) and drives a third inverter (devices 68/69) with an output signal (Vcomp) which represents the comparison result of Vin to the second inverter's threshold voltage (i.e., Vref). The third inverter outputs signal Vout which is the logical representation of the input signal in response to Vcomp. Although the receiver shown in FIG. 1 provides the accuracy of a differential receiver by using a reference voltage to establish its threshold voltage, these types of receivers dissipate power no matter what level the input signal is at as well as requiring a relatively large number of elements to provide this accuracy.
The present invention is a receiver that provides the accuracy of a differential receiver while significantly reducing power dissipation and the number of components typically required to obtain this accuracy.